1. Field of the Invention
The present invention relates to an ESD (Electrostatic Discharge) protection circuit, and more particularly to an ESD protection circuit capable of bypassing electrostatic charges under ESD stress condition by using low-voltage-tolerant components.
2. Description of the Prior Art
Because of reduction in dimension as well as significant improvement in precision, advanced electronic devices, especially those tiny elements thereinside, are sensitive to ESD and need to be properly protected therefrom. Thus, most high precision electronic devices provide additional ESD protection circuits to guard internal components against accidental ESD damage which is caused from unexpected contact with some object around or a human body.
FIG. 1 shows the I-V (current-voltage) characteristic curve of a conventional stacked NMOS (Negative Metal Oxide Semiconductor) ESD protection circuit, where the X-axis represents the drain-to-source voltage and the Y-axis represents the drain current. As shown in FIG. 1, when the voltage across drain and source gradually accumulates, the drain current increases correspondingly. As soon as the drain-to-source voltage is going to exceed a trigger voltage, it starts to experience a snapback session due to the “punch through” effect. The snapback session goes on until the drain-to-source voltage reaches down to a holding voltage. After that, the drain-to-source voltage increases smoothly and so does the drain current. The difference between the trigger voltage level and the holding voltage level is known as the snap-back region.
As can be noted from above description, when the ESD voltage is greater than the trigger voltage, the stacked NMOS functioning as an ESD protection circuit will be activated, a current will thus flow through the stacked NMOS and the electrostatic charges will bypass therethrough to the ground. Internal components of electronic devices are therefore protected from being damaged by an ESD. A limitation of conventional stacked NMOS ESD protection circuit is, however, when the electrostatic voltage is under the trigger voltage, the ESD protection circuit will fail to be activated. The electrostatic charges will consequently be kept in the electronic device and become a potential damage source to the device.
FIG. 2 shows a conventional stacked NMOS ESD protection circuit embedded in an integrated circuit (or IC). The integrated circuit works under mixed-voltage sources, say Vdd and Vcc, internally such that interfacing of semiconductor chips and sub-systems operating in different internal voltage levels can be achieved. As shown in FIG. 2, an I/O pad is connected with the internal circuit and the drain of the first NMOS (NMOS1). The gate and source of NMOS1 are respectively coupled with the voltage input terminal Vdd and the source of the second NMOS (NMOS2). The gate of NMOS2 is coupled to another voltage input terminal Vcc and the source of NMOS2 is grounded.
In FIG. 2, NMOS1 and NMOS2 are stacked in a cascade configuration such that a common diffusion region formed in the node between them. The structure of the stacked NMOS is equivalent to a parasite lateral bipolar junction transistor (hereinafter “LBJT”). When the electrostatic voltage is higher than a trigger voltage, the parasite LBJT will be activated and electrostatic charges inside will be discharged therethrough. As mentioned above, however, when the electrostatic voltage is not high enough, the LBJT will fail to be activated. As the bypassing path is still disabled, the electrostatic charges will keep residing in the integrated circuit and finally damage the MOS (Metal Oxide Semiconductor) gate oxide in the I/O buffer inside the I/O pad. Since the breakdown voltage of an MOS gate oxide will become lower in a mixed-voltage I/O circuit, the gate oxide is readily damaged by the accumulated electrostatic charges.
In view of above limitation in a conventional ESD protection circuit, there is a need to provide an ESD protection circuit which is more sensitive to electrostatic charges such that a lower trigger voltage can be achieved to have a better ESD protection for an integrated circuit.